Semiconductor dice are typically fabricated in wafer form. A silicon wafer undergoes a series of well known processing steps to fabricate a plurality of dice on the wafer. After fabrication, the individual die are separated by cutting or sawing the wafer along the scribe lines. The individual die are then encapsulated in a package. After a new die is designed and fabricated, it will often undergo a series of tests to debug the device. The die is also often subjected to electrical testing to determine if it operates within the intended design parameters. Electrical parameters, such as clock speed or frequency, signal rise and fall times, overshoot and undershoot, bandwidth, the skew between input/output pins, etc. are all tested under various conditions to determine if the device is operating within its design specifications.
One type of package used in the semiconductor industry is called a Small Outline Transistor (SOT) package. A SOT Package is typically used for very small die, for example, ranging from 5,814 or smaller to 36,920 or larger square mills (3.6 to 23 square mm). The type of die used in SOT packages include circuits such as power regulators, power management chips, temperature sensors, and the like.
A typical SOT package includes a die mounted onto a die attached pad of a lead frame. The die attach pad is usually connected to a ground lead of the lead frame so that the back surface of the die is electrically grounded. Wire bonds are formed between contract pads on the die and other leads on the lead frame. These leads are used to provide power and signals to and from the die. The entire structure, including the die, die pad, wire bonds and leads are encapsulated in a molding compound.
After semiconductor devices are packaged, they are typically debugged. A device is debugged for a several reasons, usually either for failure analysis or reliability testing. Before a product is released, the device will typically be subject to a host of electrical tests to make sure that it performs to specification. If a product fails in the field, the semiconductor vendor will typically want to analyze the device and identify any design or manufacturing defects.
SOT die are difficult to debug for a number of reasons. SOT packages are typically so small, it is difficult to access the die within the package. Furthermore, even if the top surface of the die can be accessed, the multiple levels of metal interconnect and dielectric layers found on most die makes it difficult to access the underlying circuitry. It is therefore often easier to access the circuitry from the back surface of the die. To do so, however, it often requires the removal of the die attached pad which is electrically coupled to ground. With the back surface of the die not grounded, the circuitry on the die may not operate properly. Electrical testing and evaluation of the circuitry on the die is therefore problematic.
A process to de-package a SOT package and to ground the die so that the circuitry on the die can be accessed and properly tested and debugged is therefore needed.